(1) Field of the Invention
The present invention relates to a lead frame, an electronic component including the lead frame, and a manufacturing method thereof, and relates in particular to a lead frame used for internal wiring within a device package, for connecting the device and external wiring, an electronic component including the lead frame and a manufacturing method thereof.
(2) Description of the Related Art
In recent years, as cellular phones and digital appliances, is such as DVD apparatuses and digital TVs, have become more downsized, sophisticated, and multifunctional, semiconductors and electronic components used in digital appliances are expected to be further thinned, miniaturized, and high-densified, while cost reduction is required of the packages used in semiconductor devices and electronic components.
Packages used in semiconductor devices and electronic components include, for example, a package using a multilayer wiring board on which semiconductor chips and electronic components are stacked in layers.
FIG. 1 is a cross-sectional view of a package 800 using a multilayer wiring board on which devices are stacked.
The package 800 includes: a metal wire 806, encapsulation resin 807, a device 809, a wiring board 813, and an external terminal 816.
The wiring board 813 is made up of multiple layers, including internal wiring layers 817 and via holes 819. Here, the internal wiring layers 817 are connected to through holes, that is, the via holes 819.
The wiring board 813 has a device 809 stacked on the superior surface.
External terminals 816 are formed on both surfaces of the wiring board 813 as upper and lower terminals. The external terminals 816, for example, are solder bumps. In addition, the external terminals 816 are electrically connected, through the via holes 819, to the internal wiring layers 817.
The device 809, for example, is a semiconductor chip. The device 809 is electrically connected to the internal wiring layers 817 through the metal wire 806. In addition, the device 809 and the metal wire 806 provided on the surface of the wiring board 813 are sealed with the encapsulation resin 807. On the surface of the wiring board 813, external terminals 816 that serve as the upper terminals are formed on the periphery of the encapsulation resin.
Although having an advantage in the degree of freedom in wiring layouts and so on, organic boards have nevertheless lower connection reliability, as compared to lead frames, in terms of humidity resistance and so on. In addition, when using multilayer wiring boards, it is not possible to achieve cost reduction for reasons of increased costs and so on.
Thus, various suggestions are made concerning the package using a lead frame including upper and lower external terminals (for example, Patent References 1 to 3).
Japanese Unexamined Patent Application Publication No. 2007-27526 (Patent Reference 1) describes use of a lead frame or a wiring board on which terminals, the lower surfaces of which serve as external terminals, are formed, and stud bumps are formed on the upper surface of such terminals. The Patent Reference 1 suggests a semiconductor-device package including upper and lower terminals and a manufacturing method thereof, in which the tips of the stud bumps, exposed on the upper surface of the package, serve as external terminals for the upper surface of the package.
Japanese Patent No. 3388609 (Patent Reference 2) describes an L-shaped lead portion placed and secured onto an adhesion tape. On the lead portion, a semiconductor chip is mounted. The L-shaped lead portion and the semiconductor chip are encapsulated with resin. The Patent Reference 2 suggests a semiconductor-device package including external terminals that serve as upper and lower terminals for the package through exposure of the upper and lower portions of the lead onto the surface of the encapsulating resin.
Japanese Unexamined Patent Application Publication No. 2007-141994 (Patent Reference 3) suggests a semiconductor-device package using a lead frame including upper and lower terminals. In addition, the external terminals on the upper side of the package are processed after the package is separated into each region corresponding to each semiconductor device.
Such conventional packages, however, have the following problems.
The Patent Reference 1 describes that the stud bumps are formed on the upper surfaces of the terminals formed in the lower-surface side of the package in the semiconductor device. However, the upper surfaces of the terminals, on which the stud bumps are formed, are small in area. In addition, it is difficult to control the height of the stud bumps such that the areas of the external terminals exposed on the upper surface of the package are evenly sized. Thus, the area size of the external terminals exposed on the upper surface of the package becomes uneven. Therefore, such external terminals have lower connection reliability and unstable strength when connected to a wiring board or a device. Furthermore, in an embodiment using a board, intra-board wiring and a land for a via hole for ensuring electrical continuity are internally formed in the substrate; however, there is a possibility that reliability might decrease due to the inclusion of plural connection parts for connecting the intra-board wiring and the land for a via hole.
The Patent Reference 2 describes that the L-shaped lead portion is formed vertically through the package in the semiconductor device. Plural packages and devices are stacked on the package. The package, and the plural packages and devices stacked on the package are layered through the L-shaped lead portion and electrically connected to each other through the L-shaped lead portion. Such an L-shaped lead portion, through which the packages and devices are stacked and electrically connected, is made of a hard material such as metal. Therefore, it is not possible to reduce bending stress and thermal stress on the L-shaped lead portion, thus significantly decreasing the connection reliability of products made up of packages and devices stacked in layers. In addition, every L-shaped lead portion in each stacked package is disposed at the same position in the stacking direction, and therefore it is difficult to change the design of the L-shaped lead portion, that is, the terminal position of each stacked package.
Patent Reference 3 discloses the processing of external terminals that serve as upper and lower terminals. However, the external terminals on the upper side of the package are processed after the lead frame is separated into each region corresponding to each semiconductor device. After the processing, the terminals on the upper side of the package are suspended in the air having the ends open, and this makes assembly difficult; that is, the manufacturing is not easy. In addition, since the upper-side terminals that serve as external terminals of the package and to be resin-encapsulated are not secured, there is a possibility that the upper-side terminals might be buried in the resin. Furthermore, in terms of resin encapsulation, no substantial manufacturing method is disclosed in detail.
Here, a common lead frame shall be described referring to the Quad Flat Non-Lead Package (QFN).
FIGS. 2A and 2B are diagrams showing a common lead frame used for the QFN for collective encapsulation molding. Here, the QFN refers to a semiconductor-device package which includes a semiconductor chip or the like connected to a metal lead by wire bonding, and which includes only a single line of leads provided as external terminals for implementation that appear from the molded body on the four sides, the bottom surface, or each side of the bottom surface of the package.
FIG. 2A is a plan view of a common lead frame used in the QFN. FIG. 2B is a cross-sectional view of a resin-encapsulated QFN before separation.
The QFN before separation includes a die pad 903, a metal wire 906, encapsulation resin 907, and a device 909.
A lead frame 900 includes a die pad 903, a separation frame 914, a suspension lead 915, and a terminal 916.
In FIG. 2A, a region shown by alternate long and short dash lines is the region to be a semiconductor device.
The lead frame 900 is used for the QFN for collective encapsulating molding, with a plurality of regions that is to be semiconductor devices being provided in a matrix.
The separation frame 914 is formed as a metal portion near the boundary of the adjoining semiconductor-device regions. To the separation frame 914, the suspension lead 915 supporting the die pad 903 and the terminal 916 are connected.
FIG. 2B is a diagram corresponding to the A-A′ cross section of the lead frame 900.
In the QFN before separation, a device 909 is mounted on the die pad 903, and the electrodes of the device 909 are electrically connected by the metal wire 906 to the terminal 916.
In addition, in the QFN before separation, the device 909 and the metal wire 906 are sealed with the encapsulation resin 907 at the side to which the metal wire 906 of the terminal 916 is connected.
In the QFN, the separation frame 914 is cut off with a blade along a separation line 908. However, when cutting off the separation frame 914 with a blade, the blade is under stress since the entire separation frame 914 is made of metal. This shortens the blade life as a result of blade breakage and so on, causing unnecessary increases in costs. In addition, metal burrs are generated in the cut surfaces at which the separation frame 914 is cut off with the blade. This causes the problem of decreased reliability, such as contact failure occurring at adjacent terminals 916.